An NMOSFET is a very effective ESD protection device. In one application, it is used as the pull down transistor of a CMOS buffer to drive an output voltage for an external device. In this type of application, the gate of the NMOSFET is connected to an input drive signal.
In another common NMOSFET application, the gate is electrically connected to ground, and the NMOSFET is used as an ESD protection device for an input pin or a power bus during an ESD event.
The ESD protective action of an NMOSFET is based on the device's snap-back mechanism, which enables the NMOSFET to conduct a high level of ESD current between its drain and source. This occurs when a strong electric field across the depletion region in the drain substrate junction becomes high enough to begin avalanche breakdown, which in turn causes impact ionization, resulting in the generation of both minority and majority carriers. The minority carriers flow toward the drain contact, and the majority carriers flow toward the substrate/p-well contact, causing a local potential build up across the current path in the p-well substrate. When the local substrate potential is 0.6V higher than an adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction then injects minority carriers (electrons) into the p-well, and these carriers eventually reach the drain junction to further enhance the impact ionization effect (see "ESD in Silicon Integrated Circuits," by A. Amerasekera and C. Duvvury, Chap. 3, Sec. 1., John Wiley & Sons, 1995). Eventually, the NMOSFET reaches a low impedance (snap-back) state, which enables it to conduct a large amount of ESD current.
When a multi-gate-finger MOSFET is used as a high current-drive output buffer, output overshoot noise spikes are frequently generated by the switching action of the CMOS output stage. Various prior art techniques have been developed to suppress this type of noise in high current-drive CMOS output buffers (see U.S. Pat. Nos. 4,949,139, by Korsh et al; 4,638,187, by Boler et al; and 4,725,747, by Stein et al). Typically, the prior art has involved multi-gate-finger MOSFET structures, with poly-gate fingers serially connected, or with resistors connected between the poly-gate fingers, to increase the gate signal RC delay. Because of this gate signal delay, the individual MOSFETs associated with each poly-gate finger are turned on (or off) sequentially, and the output signal overshoot, or spiking, is reduced through time distribution. On the other hand, this type of multi-gate-finger MOSFET structure has a distinct disadvantage with respect to ESD protection, since only a portion of the total number of gate fingers may turn on during an ESD event. As a result, the size of the CMOS buffer is effectively reduced during an ESD event, and the ESD performance is proportionately degraded.
For example, in a typical multi-gate-finger NMOS structure, as shown in FIGS. 2a and 2b, the poly gate fingers may not all turn on during an ESD event, even though they are all commonly connected to a metal bus. That is, if the first few gate fingers reach their snap-back low impedance mode before the remaining fingers, the drain terminal to source terminal voltage is reduced to a value, called the snap-back voltage, which is less than the trigger voltage of the NMOS device. This has the effect of preventing the remaining gate fingers from being turned on. As a result, only a partial number of the gate fingers are available to absorb the ESD energy. Therefore, the ESD protection provided by the NMOSFET is significantly reduced.
When a MOSFET gate finger is triggered during an ESD event, the entire finger turns on.
This is due to the previously described cascading effect of the impact ionization and snap-back process along the entire gate finger. Moreover, experimental data indicates that a long-gate-finger structure (e.g. 100 um.times.2), as shown in FIG. 3, has better ESD performance than a short-gate-finger structure (e.g. 20 um.times.10), of the type shown in FIG. 2a, where both structures have the same total gate width of 200 um. That is, during an ESD event, the long-finger NMOSFET structure will have either one or two gate fingers (50% to 100% of total gate width) turned on, while the short-finger NMOSFET may only have a few fingers (out of 10) turned on, with each finger being only 10% of the total gate width. In addition, the RC delay associated with a long gate finger is very effective in suppressing overshoot noise in a high current-drive buffer application. For manufacturing purposes, however, layout area is typically at a premium, and a conventional long-finger structure may not fit into the designated layout area. Therefore, both multi-gate-finger (short) and long-gate-finger (long) types of structures are used, depending on physical and electrical priorities.
A commonly used multi-gate-finger structure is shown in FIG. 4, where the poly-gate fingers are connected by a poly-gate bus, rather than the metal bus of FIG. 2a.
One prior art technique for improving the uniform turn on of such a multi-gate-finger NMOSFET structure uses a gate coupled technique, as shown in FIG. 5, and as described in "ESD in Silicon Integrated Circuits," by A. Amerasekera and C. Duvvury, Chap. 4, Sec. 2., John Wiley & Sons, 1995. In this configuration, the drain is connected to either VDD or the buffer output line, and the gate is coupled to the drain via a capacitor C, and is also connected to ground via a resistor R. The coupling capacitor C and the RC time constant of the circuit cause the gate potential to rise to 1 to 2v during the first 5 to 10 ns of an ESD event. The positive gate voltage reduces the triggering threshold of the NMOSFET, thereby enabling a more uniform turn-on of the gate fingers. This method, however, has the disadvantage of requiring additional layout area for the coupling capacitor and the resistor. In addition, since the gate is connected to ground through a resistor R, this configuration is not particularly well suited for an output buffer application.
Another type of prior art multi-gate-finger structure, as described in U.S. Pat. Nos. 4,725,747 and 4,949,139, uses the gate resistance in combination with the MOSFET RC delay to sequentially cause the MOSFET gate fingers to be turned on or off. This sequential turn on/turn off technique suppresses the noise spikes in a high current-drive output buffer through time distribution. FIG. 6 shows this type of prior art configuration, where the poly-gate fingers are serially connected into a serpentine-like gate structure in order to increase the gate signal RC delay.
With respect to ESD uniform turn on, however, this prior art serpentine gate structure is essentially equivalent to a conventional multi-gate-finger structure (FIG. 4), since each gate finger extends beyond the diffusion area and into the field oxide region. Therefore, as described above, this configuration does not provide optimum ESD protection because of its non-uniform turn on characteristics, in that only a partial number of gate fingers may turn on during an ESD event.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art with respect to MOSFET ESD protection. It is a further object of the present invention to retain the desirable noise suppression attributes of the multi-gate-finger structure, while at the same time providing an inventive improvement in MOSFET ESD performance.